Operating Modes

The mode of the timer is controlled by the MODE bits of the T2HLT register. Edge-Triggered modes require six Timer clock periods between external triggers. Level-Triggered modes require the triggering level to be at least three Timer clock periods long. External triggers are ignored while in debug mode.

Table 1. Operating Modes Table
Mode MODE<4:0> Output

Operation

 Operation Timer Control
<4:3> <2:0> Start Reset Stop
Free

Running Period

 00 000 Period Pulse Software gate (Figure 1) ON = 1 — ON = 0
001 Hardware gate, active-high

(Figure 1)

 ON = 1 and

TMRx_ers = 1

 — ON = 0 or

TMRx_ers = 0
010 Hardware gate, active-low ON = 1 and

TMRx_ers = 0

 — ON = 0 or

TMRx_ers = 1
011 Period

Pulse

with

Hardware

Reset

 Rising or falling edge Reset ON = 1 TMRx_ers ↕ ON = 0
100 Rising edge Reset (Figure 1) TMRx_ers ↑
101 Falling edge Reset TMRx_ers ↓
110 Low level Reset TMRx_ers = 0 ON = 0 or

TMRx_ers = 0
111 High level Reset (Figure 1) TMRx_ers = 1 ON = 0 or

TMRx_ers = 1
One-shot 01 000 One-shot Software start (Figure 1) ON = 1 — ON = 0

or

Next clock after

TMRx = PRx

(Note 2)
001 Edge

Triggered Start

(Note 1)

 Rising edge start (Figure 1) ON = 1 and

TMRx_ers ↑

 —
010 Falling edge start ON = 1 and

TMRx_ers ↓

 —
011 Any edge start ON = 1 and

TMRx_ers ↕

 —
100 Edge

Triggered Start

and

Hardware Reset

(Note 1)

 Rising edge start and

Rising edge Reset (Figure 1)

 ON = 1 and

TMRx_ers ↑

 TMRx_ers ↑
101 Falling edge start and

Falling edge Reset

 ON = 1 and

TMRx_ers ↓

 TMRx_ers ↓
110 Rising edge start and

Low level Reset (Figure 1)

 ON = 1 and

TMRx_ers ↑

 TMRx_ers = 0
111 Falling edge start and

High level Reset

 ON = 1 and

TMRx_ers ↓

 TMRx_ers = 1
Mono-stable 10 000 Reserved
001 Edge

Triggered

Start

(Note 1)

 Rising edge start

(Figure 1)

 ON = 1 and

TMRx_ers ↑

 — ON = 0

or

Next clock after

TMRx = PRx

(Note 3)
010 Falling edge start ON = 1 and

TMRx_ers ↓

 —
011 Any edge start ON = 1 and

TMRx_ers ↕

 —
Reserved 100 Reserved
Reserved 101 Reserved
One-shot 110 Level

Triggered

Start

and

Hardware Reset

 High level start and

Low level Reset (Figure 1)

 ON = 1 and

TMRx_ers = 1

 TMRx_ers = 0 ON = 0 or

Held in Reset

(Note 2)
111 Low level start &

High level Reset

 ON = 1 and

TMRx_ers = 0

 TMRx_ers = 1
Reserved 11 xxx Reserved
 
Note:
  1. 1.If ON = 0 then an edge is required to restart the timer after ON = 1.
  2. 2.When T2TMR = T2PR then the next clock clears ON and stops T2TMR at 00h.
  3. 3.When T2TMR = T2PR then the next clock stops T2TMR at 00h but does not clear ON.
Parent topic: Timer2 Module