In Slave mode, an external Slave Select signal can be used to synchronize communication with the master device. The Slave Select line is held in its Inactive state (high by default) until the master device is ready to communicate. When the Slave Select transitions to its Active state, the slave knows that a new transmission is starting.
When the Slave Select goes false at the end of the transmission, the receive function of the selected SPI slave device returns to the Inactive state. The slave is then ready to receive a new transmission when the Slave Select goes true again.
The Slave Select signal is received on the SS input pin. This pin is selected with the SPIxSSPPS register (refer to the “PPS Inputs” section). When the input on this pin is true, transmission and reception are enabled, and the SDO pin is driven. When the input on this pin is false, the SDO pin is either tri-stated (if the TRIS bit associated with the SDO pin is set) or driven to the value of the LAT bit associated with the SDO pin (if the TRIS bit associated with the SDO pin is cleared). The SCK input is ignored when the SS input is false.
If the SS input goes false, while a data transfer is still in progress, it is considered a Slave Select fault. The SSFLT bit indicates whether such an event has occurred. The transfer counter value determines the number of bits in a valid data transfer (see Transfer Counter for more details).
The Slave Select polarity is controlled by the SSP bit. When SSP is set (its default state), the Slave Select input is active-low, and when it is cleared, the Slave Select input is active-high.
The Slave Select for the SPI module is controlled by the SSET bit. When SSET is cleared (its default state), the Slave Select will act as described above. When the bit is set, the SPI module will behave as if the SS input is always in its Active state.
When SSET is set, the effective SS_in signal is always active. Hence, the SSFLT bit may be disregarded.