The TAP controller is a 16-state finite state machine that controls the operation of
the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system. The
state transitions depicted in Figure 2 depend on the signal present on TMS (shown adjacent to each state
transition) at the time of the rising edge at TCK. The initial state after a Power-on
Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all Shift
Registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG
interface is:
- At the TMS input, apply the sequence
1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register –
Shift-IR state. While in this state, shift the 4 bits of the JTAG instructions into
the JTAG instruction register from the TDI input at the rising edge of TCK. The TMS
input must be held low during input of the 3 LSBs in order to remain in the Shift-IR
state. The MSB of the instruction is shifted in when this state is left by setting
TMS high. While the instruction is shifted in from the TDI pin, the captured
IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction selects a
particular Data Register as path between TDI and TDO and controls the circuitry
surrounding the selected Data Register.
- Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction
is latched onto the parallel output from the Shift Register path in the Update-IR
state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the
state machine.
- At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the
Shift Data Register – Shift-DR state. While in this state, upload the selected Data
Register (selected by the present JTAG instruction in the JTAG Instruction Register)
from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR
state, the TMS input must be held low during input of all bits except the MSB. The
MSB of the data is shifted in when this state is left by setting TMS high. While the
Data Register is shifted in from the TDI pin, the parallel inputs to the Data
Register captured in the Capture-DR state is shifted out on the TDO pin.
- Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected
Data Register has a latched parallel-output, the latching takes place in the
Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for
navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered between
selecting JTAG instruction and using Data Registers, and some JTAG instructions may
select certain functions to be performed in the Run- Test/Idle, making it unsuitable as
an Idle state.
Note: 1. Independent of the initial state of the TAP Controller, the Test-Logic-Reset state
can always be entered by holding TMS high for 5 TCK clock periods.
For detailed information on the JTAG specification, refer to the literature
listed in Bibliography.