ATmega324PB Boundary-scan Order

The table below shows the Scan order between TDI and TDO when the Boundary-scan Chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A are scanned in the opposite bit order of the other ports.

Exceptions from the rules are the scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. In Figure 1, PXn. Data corresponds to FF0, PXn. Control corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.

Table 1. ATmega324PB Boundary-scan Order
Bit Number	Signal Name	Module
58	PB7.Data	Port B
57	PB7.Control	Port B
56	RSTT	Reset Logic (Observe Only)
55	PE0.Data	Port E
54	PE0.Control
53	PE1.Data
52	PE1.Control
51	PE2.Data
50	PE2.Control
49	PE3.Data
48	PE3.Control
47	PE4.Data
46	PE4.Control
45	PE5.Data
44	PE5.Control
43	PE6.Data
42	PE6.Control
41	PE7.Data
40	PE7.Control
39	PD0.Data	Port D
38	PD0.Control
37	PD1.Data
36	PD1.Control
35	PD2.Data
34	PD2.Control
33	PD3.Data
32	PD3.Control
31	PD4.Data
30	PD4.Control
29	PD5.Data
28	PD5.Control
27	PD6.Data
26	PD6.Control
25	PD7.Data
24	PD7.Control
23	PC0.Data	Port C
22	PC0.Control
21	PC1.Data
20	PC1.Control
19	PC6.Data
18	PC6.Control
17	PC7.Data
16	PC7.Control
15	PA7.Data	Port A
14	PA7.Control
13	PA6.Data
12	PA6.Control
11	PA5.Data
10	PA5.Control
9	PA4.Data
8	PA4.Control
7	PA3.Data
6	PA3.Control
5	PA2.Data
4	PA2.Control
3	PA1.Data
2	PA1.Control
1	PA0.Data
0	PA0.Control