To ensure that masters with latency requirements get sufficient priority when accessing RAM, the different masters can be configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any access to the RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration is shown in below.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |
If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be minimum latency of one cycle for the RAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master and second, a static priority given by Table 3. The lowest port ID has the highest static priority.
The MTB has fixed QoS level HIGH (0x3) and the DSU has fixed QoS level LOW (0x1).
The CPU QoS level can be written/read at address 0x41007110, bits [1:0]. Its reset value is 0x0.
Refer to different master QOSCTRL registers for configuring QoS for the other masters (DMAC).