WEXCTRL

Name:: WEXCTRL
Offset:: 0x14
Reset:: 0x00000000
Access:: PAC Write-Protection, Enable-Protected

Bit31	30	29	28	27	26	25	24
DTHS[7:0]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset0	0	0	0	0	0	0	0
Bit23	22	21	20	19	18	17	16
DTLS[7:0]
AccessR/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset0	0	0	0	0	0	0	0
Bit15	14	13	12	11	10	9	8
				DTIEN3	DTIEN2	DTIEN1	DTIEN0
Access				R/W	R/W	R/W	R/W
Reset				0	0	0	0
Bit7	6	5	4	3	2	1	0
						OTMX[1:0]
Access						R/W	R/W
Reset						0	0

Bits 31:24 – DTHS[7:0]: Dead-Time High Side Outputs Value

Dead-Time High Side Outputs Value

This register holds the number of GCLK_TCC clock cycles for the dead-time high side.

Bits 23:16 – DTLS[7:0]: Dead-time Low Side Outputs Value

Dead-time Low Side Outputs Value

This register holds the number of GCLK_TCC clock cycles for the dead-time low side.

Bits 1:0 – OTMX[1:0]: Output Matrix

Output Matrix

These bits define the matrix routing of the TCC waveform generation outputs to the port pins, according to Table 1.

Bits 11,10,9,8 – DTIENx : Dead-time Insertion Generator x Enable

Dead-time Insertion Generator x Enable

Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform respectively.

Value	Description
0	No dead-time insertion override.
1	Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x] signal.