I2CxADR3
I2C Address 3 Register(1)
11110’
bit pattern used in the 10-bit address high byte is defined by the
I2C Specification. It is up to the user to define these bits.
These bit values are compared to the received address by hardware to
determine a match. The bit pattern transmitted by the master must be the
same as the slave address’s bit pattern used for comparison or a match will
not occur.| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADR[6:0] | |||||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset1 | 1 | 1 | 1 | 1 | 1 | 1 | |
I2C Slave Address 3
| Name | Description |
|---|---|
7-bit Slave/Multi-Master modes (MODE = 000 or
110): |
7-bit slave address 3 |
7-bit Slave/Multi-Master modes with Masking
(MODE = 001 or
111): |
7-bit slave address mask for I2CxADR2 |
10-bit Slave mode (MODE =
010): |
ADR[7:3]: Bit pattern (11110) as defined by the
I2C Specification(1)ADR[2:1]: Two Most Significant bits of second 10-bit address |
10-bit Slave mode with Masking (MODE =
011): |
ADR[7:3]: Bit pattern (11110) as defined by the
I2C Specification(1)ADR[2:1]: Two Most Significant bits of 10-bit address mask |