I2CxCON0

I2C Control Register 0
Note:
  1. 1.SDA and SCL pins must be configured as open-drain I/Os and use either internal or external pull-up resistors.
  2. 2.SDA and SCL signals must configure both the input and output PPS registers for each signal.
  3. 3.CSTR can be set by multiple hardware sources; all sources must be addressed by user software before the SCL line can be released.
  4. 4.SMA is set on the same SCL edge as CSTR for a matching received address.
  5. 5.In this mode, ADRIE should be set, allowing an interrupt to clear the BCLIF condition and the ACK of a matching address.
  6. 6.In 10-bit Slave mode (when ABD = 1), CSTR will be set when the high address has not been read from I2CxRXB before the low address is shifted in.
Name:
I2CxCON0
Address:
0x0294
Reset:
Access:
Bit76543210
ENRSENSCSTRMDRMODE[2:0]
AccessR/WR/WR/W/HS/HCR/C/HS/HCRR/WR/WR/W
Reset00000000

Bit 7 – EN: I2C Module Enable(1,2)

I2C Module Enable(1,2)

ValueDescription
1 The I2C module is enabled
0 The I2C module is disabled

Bit 6 – RSEN: Restart Enable (used only when MODE = 1xx)

Restart Enable (used only when MODE = 1xx)

ValueDescription
1 Hardware sets MDR on 9th falling SCL edge (when I2CxCNT = 0 or ACKSTAT = 1)
0 Hardware issues Stop condition on 9th falling SCL edge (when I2CxCNT = 0 or ACKSTAT = 1)

Bit 5 – S: Master Start (used only when MODE = 1xx)

Master Start (used only when MODE = 1xx)

ValueNameDescription
1 MMA = 0: Set by write to I2CxTXB or S bit, hardware issues Start condition
0 MMA = 0: Cleared by hardware after sending Start condition
1 MMA = 1 and MDR = 1: Set by write to I2CxTXB or S bit, communication resumes with a Restart condition
0 MMA = 1 and MDR = 1: Cleared by hardware after sending Restart condition

Bit 4 – CSTR: Slave Clock Stretching(3)

Slave Clock Stretching(3)

ValueNameDescription
1   Clock is held low (clock stretching)
0   Enable clocking, SCL control is released
     
  SMA = 1 and RXBF = 1(6): Set by hardware on 7th falling SCL edge

User must read I2CxRXB and clear CSTR to release SCL
  SMA = 1 and TXBE = 1 and I2CxCNT != 0: Set by hardware on 8th falling SCL edge

User must write to I2CxTXB and clear CSTR to release SCL
  when ADRIE = 1(4): Set by hardware on 8th falling edge of matching received address

User must clear CSTR to release SCL
  SMA = 1 and WRIE = 1: Set by hardware on 8th falling SCL edge of received data byte

User must clear CSTR to release SCL
  SMA = 1 and ACKTIE = 1: Set by hardware on 9th falling SCL edge

User must clear CSTR to release SCL

Bit 3 – MDR: Master Data Request (Master pause)

Master Data Request (Master pause)

ValueNameDescription
1   Master state machine pauses until data is read/written (SCL is held low)
0   Master clocking of data is enabled
     
  MMA = 1 and RXBF = 1 (pause for RX): Set by hardware on 7th falling SCL edge

User must read I2CxRXB to release SCL
  MMA = 1 and TXBE = 1 and I2CxCNT != 0 (pause for TX): Set by hardware on the 8th falling SCL edge

User must write to I2CxTXB to release SCL
  RSEN = 1 and MMA = 1 and (I2CxCNT = 0 or ACKSTAT = 1) (pause for Restart): Set by hardware on 9th falling SCL edge

User must set S bit or write to I2CxTXB to release SCL and issue a Restart condition

Bits 2:0 – MODE[2:0]: I2C Mode Select

I2C Mode Select

ValueDescription
111 I2C Multi-Master mode (SMBus 2.0 Host)(5)
110 I2C Multi-Master mode (SMBus 2.0 Host)(5)
101 I2C Master mode, 10-bit address
100 I2C Master mode, 7-bit address
011 I2C Slave mode, one 10-bit address with masking
010 I2C Slave mode, two 10-bit addresses
001 I2C Slave mode, two 7-bit addresses with masking
000 I2C Slave mode, four 7-bit addresses