In a multi-master system, each master may begin to generate a clock signal as soon as the bus is idle. Clock synchronization allows all devices on the bus to use a single SCL signal.
When a high-to-low transition on SCL occurs, all active master devices begin SCL low period timing, with their clocks held low until their low hold time expires and the high state is reached. If one master’s clock signal is still low, SCL will be held low until that master reaches its high state. During this time, all other master devices are held in a Wait state (see figure below).
Once all masters have counted off their low period times, SCL is released high and all master devices begin counting their high periods. The first master to complete its high period pulls the SCL line low again.
This means that when the clocks are synchronized, the SCL low period is determined by the master with the longest SCL low period, while the SCL high period is determined by the master device with the shortest SCL high period.
