In Multi-Master mode, multiple master devices reside on the same bus. A
single device, or all devices, may act as both a master and a slave. Control of the bus
is achieved through clock synchronization and bus arbitration.
The Bus Free (
BFRE) bit is used to determine if the bus is free.
When BFRE is set (BFRE =
1), the bus is in an Idle state, allowing a
master device to take control of the bus.
In Multi-Master mode, the Address Interrupt and Hold Enable (
ADRIE) bit must be set (ADRIE =
1) and the Clock
Stretching Disable (
CSD) bit must be clear (CSD =
0), in order for
a master device to be addressed as a slave.
When a matching address is received into the receive shift register, the
SMA and the Address Interrupt Flag (ADRIF) bits are
set. Since ADRIE is also set, hardware sets the Slave Clock Stretching (
CSTR) bit, and hardware stretches the clock to allow time for
software to respond to the master device being addressed as a slave. Once the address
has been processed, software must clear CSTR to resume communication.
Important: Slave hardware has
priority over master hardware in Multi-Master mode. Master mode communication can only
be initiated when SMA = 0.