CVD operation begins with an optional precharge state, where the external capacitive sensor and the internal CHOLD capacitor are charged to known and opposite voltage levels (either VSS or VDD). The user needs to ensure that both sensors have enough time to charge completely to a known voltage level to ensure an accurate reading from the external sensor. The amount of time allocated for the precharge stage is determined by the value written to the corresponding precharge timer register (ADPRE). Reference the device data sheet to determine the size of the precharge timer register. The precharge polarity of the internal sample and hold capacitor and external sensor on the configured analog pin is determined by the value written to the PPOL bit of the appropriate ADCON register.
CVD operation can either be configured to perform one
conversion for each trigger, or two conversions for each trigger
(differential CVD). Double sampling can be enabled by setting
the DSEN bit of the appropriate ADCON register. When performing
a differential CVD operation, the A/D Inverted Precharge bit
should be enabled (IPEN = 1) to configure the
precharge and guard signals in the second conversion cycle to
precharge opposite of what was done for the first conversion. It
is also important to determine the guard ring polarity during
the precharge stage by setting the GPOL bit of the ADCON
register. Refer to ADC Module Setup for CVD Measurement, which demonstrates the
initialization of the appropriate ADC2 registers to
set up the precharge stage during a CVD operation. Refer to
Guard Ring Circuit for more information on
the Guard Ring Circuit.