Address Buffers

The I²C module has two address buffer registers, I2CxADB0 and I2CxADB1, which can be used as address receive buffers in Slave mode, address transmit buffers in Master mode, or both address transmit and address receive buffers in 7-bit Multi-Master mode (see table below). The address buffers are enabled/disabled via the Address Buffer Disable (ABD) bit.

When the ABD bit is clear (ABD = 0), the buffers are enabled, which means:

• In 7-bit Master mode, the desired slave address with the R/W value is transmitted from the I2CxADB1 register, bypassing the I²C Transmit Buffer (I2CxTXB). I2CxADB0 is unused.
• In 10-bit Master mode, I2CxADB1 holds the upper bits and R/W value of the desired slave address, while I2CxADB0 holds the lower eight bits of the desired slave address. Master hardware copies the contents of I2CxADB1 to the transmit shift register, and waits for an ACK from the slave. Once the ACK is received, master hardware copies the contents of I2CxADB0 to the transmit shift register.
• In 7-bit Slave mode, a matching received address is loaded into I2CxADB0, bypassing the I²C Receive Buffer (I2CxRXB). I2CxADB1 is unused.
• In 10-bit Slave mode, I2CxADB0 is loaded with the lower eight bits of the matching received address, while I2CxADB1 is loaded with the upper bits and R/W value of the matching received address.
• In 7-bit Multi-Master mode, the device can be both a master and a slave depending on the sequence of events on the bus. When being addressed as a slave, the matching received address with R/W value is stored into I2CxADB0. When being used as a master, the desired slave address and R/W value are loaded into the I2CxADB1 register.

When the ABD bit is set (ABD = 1), the buffers are disabled, which means:

• In Master mode, the desired slave address is transmitted from the I2CxTXB register.
• In Slave mode, a matching received address is loaded into the I2CxRXB register.