Rev G - 04/2015

Ordering Information	Added Device Identification.
I/O Multiplexing and Considerations	New sections added: SERCOM I2C Pins: Information moved from the "Type" column in Table 1 into separate table. Updated CCL column. GPIO Clusters: Moved from Absolute Maximum Ratings. TCC Configurations: Moved from TCC – Timer/Counter for Control Applications.
Memories	Updated Table 1. Updated Table 1.
PAC - Peripheral Access Controller	Register bit correction: INTFLAGAHB, INTFLAGA, INTFLAGB, INTFLAGC, STATUSA, STATUSB and STATUSC
DSU - Device Service Unit	Table 1 updated: MBIST is not available when the device is protected from the external address space.
GCLK - Generic Clock Controller	Block Diagram: GCLK_MAIN goes into the MCLK, not the PM. Signal Description: Available signals are GCLK_IO[7:0].
MCLK – Main Clock	Updated block diagram in Selecting the Synchronous Clock Division Ratio.
OSCCTRL – Oscillators Controller	Added OSC48M Calibration (CAL48M) register added (only available for Rev D silicon).
SUPC – Supply Controller	Updated VREF.SEL bit selection table. Removed references to BODCORE register and bit descriptions and updated description in VDDCORE Brown-Out Detector (BODCORE).
PM – Power Manager	Sleep modes: Removed references to IDLE0 and IDLE1. Renamed IDLE2 to IDLE.
DMAC – Direct Memory Access Controller	CTRL.CRCENABLE bit added in bit position 2.
NVMCTRL – Non-Volatile Memory Controller	CTRLB.CACHEDIS: Updated from one bit in postion 18 to two bits in position 19:18. Updated bit description and bit value settings.
SERCOM SPI – SERCOM Serial Peripheral Interface	Features: Updated references to serial clock speed in master and slave operation.
TC – Timer/Counter	Added register property "Write-Synchronized" to the CCBUFx and PERBUF registers.
TCC – Timer/Counter for Control Applications	Updated number of TCC instances from one to three. Counter Operation: 'Stop Command and Event Action' split into 'Stop Command' and 'Pause Event Action' Capture Operations: Value 0 in CAPTMIN mode is captured only in down-counting mode. Ramp Operations: RAMP2C Operation added. Compare Operations: Reorganization of section. Corrected bit names in the WAVE register: CIRCCENx -> CICCENx and CIRPEREN -> CIPEREN.
CCL – Configurable Custom Logic	Number of LUTCTRL registers changed from eight to four. Number of SEQCTRL registers changed from four to two.
AC – Analog Comparators	COMPCTRLn: SPEED bit description updated. Values 0x1 and 0x2 is reserved.
DAC – Digital-to-Analog Converter	Updated DATA register: DATA bits access corrected from read/write (R/W) to write (W).
Electrical Characteristics 85°C	Added electrical characteristics for 85°C. GPIO Clusters moved to I/O Multiplexing and Considerations.
Electrical Characteristics 105°C	Added electrical characteristics for 105°C.
Packaging Information	Updated package drawings to include GPC, drawing no. and revision letter.
Errata	Updated revision B errata: Added Errata reference 14497, 14633 and 15342. Added revision C errata. Added revision D errata.