0), I2CxADB1 is loaded with the slave high address, I2CxADB0 is loaded with the slave low address, and I2CxCNT is loaded with a count value. Once software sets the Start (S) bit, the MMA bit is set, and hardware transmits the 10-bit slave address.
Upon the 8th falling SCL edge of the transmitted address low byte, since TXBE = 1, the MDR and I2CxTXIF bits are set, and hardware stretches the clock
while the DMA loads I2CxTXB with data. Once the DMA loads I2CxTXB, the TXBE, MDR,
and I2CxTXIF bits are cleared by hardware, and the DMA waits for the next occurrence of
I2CxTXIF being set. When address buffers are disabled (ABD = 1), software must load I2CxTXB with the
slave high address to begin transmission. Once the slave high address has been
transmitted, I2CxTXIF will be set, triggering the DMA to load I2CxTXB with slave low
address. Once the DMA loads I2CxTXB with the slave low address, the TXBE, MDR, and
I2CxTXIF bits are cleared by hardware, and the DMA waits for the next occurrence of
I2CxTXIF being set.