A Stop condition occurs when SDA transitions from an Active state to an Idle state while SCL is idle. Master hardware will issue a Stop condition when it has completed its current transmission and is ready to release control of the bus. A Stop condition is also issued after an error condition occurs, such as a bus time-out, or when a NACK condition is detected on the bus.
After the ACK/NACK sequence of the final byte of
the transmitted/received packet, hardware pulls SCL low for half of an SCL period
(TSCL/2) (see figure below). After the half SCL period, hardware releases
SCL, then samples SCL to ensure it is in an Idle state (SCL =
1).
Master hardware then waits the duration of the Stop condition setup time
(TSU:STO) and releases SDA, setting the Stop Condition Interrupt Flag
(PCIF). If the Stop Condition Interrupt Enable
(PCIE) bit is also set, the generic I2CxIF is also
set. Important: At least one SCL low
period must appear before a Stop condition is valid. If the SDA line transitions low,
then high again, while SCL is high, the Stop condition is ignored and a Start condition
will be detected by the receiver.
Figure 1. Stop Condition Timing
Important:
- 1.At least one SCL low period must appear before a Stop is valid.
- 2.Refer to the “Electrical Specifications” chapter for Stop condition setup and hold times.