Register Summary

Table 1. Event System Register Summary
Offset Name Bit
Pos.                
0x00 CTRL 7:0       GCLKREQ       SWRST
0x01

...

0x03

Reserved                  
0x04 CHANNEL 7:0         CHANNEL[3:0]
0x05 15:8               SWEVT
0x06 23:16   EVGEN[6:0]
0x07 31:24         EDGSEL[1:0] PATH[1:0]
0x08 USER 7:0       USER[4:0]
0x09 15:8       CHANNEL[4:0]
0x0A Reserved                  
0x0B Reserved                  
0x0C CHSTATUS 7:0 USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0
0x0D 15:8 CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0
0x0E 23:16         USRRDY11 USRRDY10 USRRDY9 USRRDY8
0x0F 31:24         CHBUSY11 CHBUSY10 CHBUSY9 CHBUSY8
0x10 INTENCLR 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
0x11 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
0x12 23:16         OVR11 OVR10 OVR9 OVR8
0x13 31:24         EVD11 EVD10 EVD9 EVD8
0x14 INTENSET 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
0x15 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
0x16 23:16         OVR11 OVR10 OVR9 OVR8
0x17 31:24         EVD11 EVD10 EVD9 EVD8
0x18 INTFLAG 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
0x19 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
0x1A 23:16         OVR11 OVR10 OVR9 OVR8
0x1B 31:24         EVD11 EVD10 EVD9 EVD8