All I2C communication is performed in 9-bit segments consisting of an 8-bit address/data segment followed by a 1-bit acknowledgement segment. Address and data bytes are transmitted with the Most Significant bit (MSb) first. Interaction between the I2C module and other devices on the bus is controlled and monitored through several I2C Control, Status, and Interrupt registers.
1, both SDA
and SCL lines are floating to a logic high and the bus is considered ‘idle’. When the
master detects an idle bus, it transmits a Start condition, followed by the address of
the slave it intends to communicate with. The slave address can be either 7-bit or
10-bit, depending on the application design.In 7-bit Addressing mode, the Least Significant bit (LSb) of the 7-bit slave
address is reserved for the Read/not Write (R/W) bit, while in
10-bit Addressing mode, the LSb of the high address byte is reserved as the
R/W bit. If the R/W bit is clear
(R/W = 0), the master intends to read
information from the slave. If R/W is set
(R/W = 1), the master intends to write
information to the slave. If the addressed slave exists on the bus, it must respond with
an Acknowledgement (ACK) condition.
Once a slave has been successfully addressed, the master will continue to receive data from the slave, write data to the slave, or a combination of both. Data is always transmitted Most Significant bit (MSb) first. When the master has completed its transactions, it can either issue a Stop condition, signaling to the slave that communication is to be terminated, or a Restart condition, informing the bus that the current master wishes to hold the bus to communicate with the same or other slave devices.