Restart Condition Timing

A Restart condition is identical to a Start condition. A master device may issue a Restart instead of a Stop condition if it intends to hold the bus after completing the current data transfer. A Restart condition occurs when the Restart Enable (RSEN) bit is set (RSEN = 1), either I2CxCNT is zero (I2CxCNT = 0) or ACKSTAT is set (ACKSTAT = 1), and either master hardware (ABD = 1) or user software (ABD = 0) sets the Start (S) bit.

When the Start bit is set, master hardware releases SDA (SDA floats high) for half of an SCL clock period (T_SCL/2), and then releases SCL for another half of an SCL period, then samples SDA (see figure below). If SDA is sampled low while SCL is sampled high, a bus collision has occurred. In this case, the Bus Collision Detect Interrupt Flag (BCLIF) is set, and if the Bus Collision Detect Interrupt Enable (BCLIE) bit is also set, the generic I2CxEIF is set, and the module goes idle. If SDA is sampled high while SCL is also sampled high, master hardware issues a Start condition. Once the Restart condition is detected on the bus, the Restart Condition Interrupt Flag (RSCIF) is set by hardware. If the Restart Condition Interrupt Enable (RSCIE) bit is set, the generic I2CxIF is also set.