Clock stretching occurs when a slave device holds the SCL line low to pause
bus communication. A slave device may stretch the clock to allow more time to process
incoming data, prepare a response for the master device, or to prevent receive overflow
or transmit underflow conditions. Clock stretching is enabled by clearing the Clock
Stretch Disable (
CSD) bit, and is only available in Slave and Multi-Master
modes.
When clock stretching is enabled (CSD =
0), the Slave Clock
Stretching (
CSTR) bit can be used to determine if the clock is
currently being stretched. While the slave is actively stretching the clock, CSTR is set
by hardware (CSTR =
1). Once the slave has completed its current
transaction and clock stretching is no longer required, either module hardware or user
software must clear CSTR to release the clock and resume communication.