Clock Stretching for Other Slave Operations

The I²C module provides three Interrupt and Hold Enable features:

Address Interrupt and Hold Enable
Data Write Interrupt and Hold Enable
Acknowledge Status Time Interrupt and Hold Enable

When clock stretching is enabled (CSD = 0), the Interrupt and Hold Enable features provide an interrupt response, and stretches the clock to allow time for address recognition, data processing, or an ACK/NACK response.

The Address Interrupt and Hold Enable feature will generate an interrupt event and stretch the SCL line when a matching address is received. This feature is enabled by setting the Address Interrupt and Hold Enable (ADRIE) bit. When enabled ADRIE( = 1), the CSTR bit and the Address Interrupt Flag (ADRIF) bit are set by module hardware, and the SCL line is stretched following the 8th falling SCL edge of a received matching address. Once the slave has completed processing the address, software determines whether to send an ACK or a NACK back to the master device. Slave software must clear both the ADRIF and CSTR bits to resume communication.

Important: In 10-bit Slave Addressing mode, clock stretching occurs only after the slave receives a matching low address byte, or a matching high address byte with the R/W bit = 1 (Master read) while the Slave Mode Active (SMA) bit is set SMA( = 1). Clock stretching does not occur after the slave receives a matching high address byte with the R/W bit = 0 (Master write).

The Data Write Interrupt and Hold Enable feature provides an interrupt event and stretches the SCL signal after the slave receives a data byte. This feature is enabled by setting the Data Write Interrupt and Hold Enable (WRIE) bit. When enabled (WRIE = 1), module hardware sets both the CSTR bit and the Data Write Interrupt Flag (WRIF) bit and stretches the SCL line after the 8th falling edge of SCL. Once the slave has read the new data, software determines whether to send an ACK or a NACK back to the master device. Slave software must clear both the CSTR and WRIF bits to resume communication.

The Acknowledge Status Time Interrupt and Hold Enable feature generates an interrupt event and stretches the SCL line after the acknowledgement phase of a transaction. This feature is enabled by setting the Acknowledge Status Time Interrupt and Hold Enable (ACKTIE) bit. When enabled ACKTIE( = 1), module hardware sets the CSTR bit and the Acknowledge Status Time Interrupt Flag (ACKTIF) bit and stretches the clock after the 9th falling edge of SCL for all address, read, or write operations. Slave software must clear both the ACKTIF and CSTR bits to resume communication.