Slave Transmission (7-bit Addressing Mode)

The following section describes the sequence of events that occur when the module is transmitting data in 7-bit Addressing mode:

  1. 1.The master device issues a Start condition. Once the Start condition has been detected, slave hardware sets the Start Condition Interrupt Flag (SCIF) bit. If the Start Condition Interrupt Enable (SCIE) bit is also set, the generic I2CxIF is also set.
  2. 2.Master hardware transmits the 7-bit slave address with the R/W bit set, indicating that it intends to read data from the slave.
  3. 3.The received address is compared to the values in the I2CxADR registers. If the slave is configured in 7-bit Addressing mode (no masking), the received address is independently compared to each of the I2CxADR0/1/2/3 registers. In 7-bit Addressing with Masking mode, the received address is compared to the masked value of I2CxADR0 and I2CxADR2.

    If an address match occurs:

    • The Slave Mode Active (SMA) bit is set by module hardware.
    • The R/W bit value is copied to the Read Information (R) bit by module hardware.
    • The Data (D) bit is cleared by hardware, indicating the last received byte was an address.
    • The Address Interrupt Flag (ADRIF) bit is set. If the Address Interrupt and Hold Enable (ADRIE) bit is set, and the Clock Stretching Disable (CSD) bit is clear, hardware sets the Slave Clock Stretching (CSTR) bit and the generic I2CxIF bit. This allows time for the slave to read either I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the slave has finished processing the address, software must clear CSTR to resume operation.
    • The matching received address is loaded into either the I2CxADB0 register or into the I2CxRXB register as determined by the Address Buffer Disable (ABD) bit. When ABD is clear (ABD = 0), the matching address is copied to I2CxADB0. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets the Receive Buffer Full Status (RXBF) bit and the I2C Receive Interrupt Flag (I2CxRXIF) bit. I2CxRXIF is a read-only bit, and must be cleared by either reading I2CxRXB or by setting the Clear Buffer (CLRBF) bit (CLRBF = 1).

    If no address match occurs, the module remains idle.

  4. 4.If the Transmit Buffer Empty Status (TXBE) bit is set (TXBE = 1), I2CxCNT has a non-zero value (I2CxCNT != 0), and the I2C Transmit Interrupt Flag (I2CxTXIF) is set (I2CxTXIF = 1), slave hardware sets CSTR, stretches the clock (when CSD = 0), and waits for software to load I2CxTXB with data. I2CxTXB must be loaded to clear I2CxTXIF. Once data is loaded into I2CxTXB, hardware automatically clears CSTR to resume communication.
  5. 5.The master device transmits the 9th clock pulse, and slave hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive overflow (RXO = 1), slave hardware automatically generates a NACK condition. NACKIF is set, and the module goes idle.
  6. 6.Upon the 9th falling SCL edge, the data byte in I2CxTXB is transferred to the transmit shift register, and I2CxCNT is decremented by one. Additionally, the Acknowledge Status Time Interrupt Flag (ACKTIF) bit is set. If the Acknowledge Status Time Interrupt and Hold Enable (ACKTIE) bit is also set, the generic I2CxIF is set, and if slave hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0). If a NACK was generated, the CSTR bit remains unchanged. Once complete, software must clear CSTR and ACKTIF to release the clock and continue operation.
  7. 7.If the slave generated an ACK and I2CxCNT is non-zero, master hardware transmits eight clock pulses, and slave hardware begins to shift the data byte out of the shift register starting with the Most Significant bit (MSb).
  8. 8.After the 8th falling edge of SCL, slave hardware checks the status of TXBE and I2CxRXB. If TXBE is set and I2CxCNT has a non-zero count value, hardware sets CSTR and the clock is stretched (when CSD = 0) until software loads I2CxTXB with new data. Once I2CxTXB has been loaded, hardware clears TXBE, I2CxTXIF, and CSTR to resume communication.
  9. 9.Once the master hardware clocks in all eight data bits, it transmits the 9th clock pulse along with the ACK/NACK response back to the slave. Slave hardware copies the ACK/NACK value to the Acknowledge Status (ACKSTAT) bit and sets ACKTIF. If ACKTIE is also set, slave hardware sets the generic I2CxIF bit and CSTR, and stretches the clock (when CSD = 0). Software must clear CSTR to resume operation.
  10. 10.After the 9th falling edge of SCL, data currently loaded in I2CxTXB is transferred to the transmit shift register, setting both TXBE and I2CxTXIF. I2CxCNT is decremented by one. If I2CxCNT is zero (I2CxCNT = 0), CNTIF is set.
  11. 11.If I2CxCNT is non-zero and the master issued an ACK on the last byte (ACKSTAT = 0), the master transmits eight clock pulses, and slave hardware begins to shift data out of the shift register.
  12. 12.Repeat steps 8 – 11 until the master has received all the requested data (I2CxCNT = 0). Once all data has been received, the master issues a NACK, followed by either a Stop or Restart condition. Once the NACK has been received by the slave, hardware sets NACKIF and clears SMA. If the NACK Detect Interrupt Enable (NACKIE) bit is also set, the generic I2C Error Interrupt Flag (I2CxEIF) is set. If the master issued a Stop condition, slave hardware sets the Stop Condition Interrupt Flag (PCIF). If the master issued a Restart condition, slave hardware sets the Restart Condition Interrupt Flag (RSCIF). If the associated interrupt enable bits are also set, the generic I2CxIF is also set.
    Important: I2CxEIF is read-only, and is cleared by hardware when all enable interrupt flag bits in I2CxERR are cleared.
Figure 1. 7-Bit Slave Mode Transmission (No Clock Stretching)
Figure 2. 7-Bit Slave Mode Transmission (ADRIE = 1)
Figure 3. 7-Bit Slave Mode Transmission (ACKTIE = 1)
Parent topic: Slave Operation in 7-Bit Addressing Modes