Master Reception (10-Bit Addressing Mode)

The following section describes the sequence of events that occur when the module is receiving data in 10-bit addressing mode:

1. 1.Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods may be used to begin communication:
   1. 1.1.When ABD is clear (ABD = 0), the address buffers, I2CxADB0 and I2CxADB1, are enabled. In this case, the address high byte and R/W bit are loaded into I2CxADB1, with R/W clear (R/W = 0). The address low byte is loaded into I2CxADB0 and the Restart Enable (RSEN) bit is set by software. After these registers are loaded, software must set the Start (S) bit to begin communication. Once the S bit is set, master hardware waits for the Bus Free (BFRE) bit to be set before transmitting the Start condition to avoid bus collisions.
   2. 1.2.When ABD is set (ABD = 1), the address buffers are disabled. In this case, the number of expected received bytes are loaded into I2CxCNT, the address high byte and R/W bit are loaded into I2CxTXB, with R/W clear (R/W = 0). A write to I2CxTXB will cause master hardware to automatically issue a Start condition once the bus is idle (BFRE = 1). Software writes to the Start bit are ignored.
2. 2.Master hardware waits for BFRE to be set, then shifts out the Start condition. Module hardware sets the Master Mode Active (MMA) bit and the Start Condition Interrupt Flag (SCIF). If the Start Condition Interrupt Enable (SCIE) bit is set, the generic I2CxIF is also set.
3. 3.Master hardware transmits the address high byte and R/W bit.
4. 4.Master hardware samples SCL to determine if the slave is stretching the clock and continues to sample SCL until the line is sampled high.
5. 5.Master hardware transmits the 9th clock pulse and receives the ACK/NACK response from the slave.
   If a NACK was received, the NACK Detect Interrupt Flag (NACKIF) is set and the master immediately issues a Stop condition.

   If an ACK was received, module hardware transmits the address low byte.

6. 6.Master hardware samples SCL to determine if the slave is stretching the clock and continues to sample SCL until the line is sampled high.
7. 7.Master hardware transmits the 9th clock pulse and receives the ACK/NACK response from the slave.
   If an ACK was received, hardware sets MDR and waits for hardware or software to set the Start bit.
   If a NACK is received, hardware sets NACKIF, and:
   1. 7.1.ABD = 0: Master generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for software to set the Start bit to generate a Restart condition.
   2. 7.2.ABD = 1: Master generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for software to load a new address into I2CxTXB. Software writes to the Start bit are ignored.

   If the NACK Detect Interrupt Enable (NACKIE) is also set, hardware sets the generic I2CxEIF bit.

8. 8.Software loads I2CxCNT with the expected number of received bytes.
9. 9.If ABD is clear (ABD = 0), software sets the Start bit. If ABD is set (ABD = 1), software writes the address high byte with R/W bit into I2CxTXB, with R/W set (R/W = 1).
10. 10.Master hardware transmits the Restart condition, which sets the Restart Condition Interrupt Flag (RSCIF) bit. If the Restart Condition Interrupt Enable (RSCIE) bit is set, the generic I2CxIF is set by hardware.
11. 11.Master hardware transmits the high address byte and R/W bit.
12. 12.Master hardware samples SCL to determine if the slave is stretching the clock and continues to sample SCL until the line is sampled high.
13. 13.Master hardware transmits the 9th clock pulse and receives the ACK/NACK response from the slave.

    If an ACK is received, master hardware receives the first seven bits of the data byte into the receive shift register.

    If a NACK is received, and:

    1. 13.1.ABD = 0: Master generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for software to set the Start bit to generate a Restart condition.
    2. 13.2.ABD = 1: Master generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for software to load a new address into I2CxTXB. Software writes to the Start bit are ignored.
14. 14.If previous data is currently in I2CxRXB (RXBF = 1) when the first seven bits are received by the receive shift register, hardware sets MDR, and the clock is stretched after the 7th falling edge of SCL. This allows software to read I2CxRXB, which clears the RXBF bit, and prevents a receive buffer overflow. Once the RXBF bit is cleared, hardware releases SCL.
15. 15.Master hardware clocks in the 8th bit of the data byte into the receive shift register, then transfers the complete byte into I2CxRXB, which sets the I2CxRXIF and RXBF bits. If I2CxRXIE is also set, hardware sets the generic I2CxIF bit. I2CxCNT is decremented by one.
16. 16.Hardware checks I2CxCNT for a zero value.
    If I2CxCNT is non-zero (I2CxCNT != 0), hardware transmits the value of the Acknowledge Data (ACKDT) bit as the acknowledgement response to the slave. It is up to user software to properly configure ACKDT. In most cases, ACKDT should be clear (ACKDT = 0), which indicates an ACK response.
    If I2CxCNT is zero (I2CxCNT = 0), hardware transmits the value of the Acknowledge End of Count (ACKCNT) bit as the acknowledgement response to the slave. CNTIF is set, and master hardware either issues a Stop condition or a Restart condition. It is up to user software to properly configure ACKCNT. In most cases, ACKCNT should be set (ACKCNT = 1), which indicates a NACK response. When hardware detects a NACK on the bus, it automatically issues a Stop condition. If a NACK is not detected, the Stop will not be generated, which may lead to a stalled bus condition.
17. 17.Master hardware receives the first seven bits of the next data byte into the receive shift register.
18. 18.Repeat Steps 14 – 17 until all expected bytes have been received.

Figure 1. 10-Bit Master Mode Reception