Master Transmission (10-Bit)

The following section describes the sequence of events that occur when the module is transmitting data in 10-bit Addressing mode:

1. 1.Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods may be used to begin communication:
   1. 1.1.When ABD is clear (ABD = 0), the address buffers, I2CxADB0 and I2CxADB1, are enabled. In this case, the address high byte is loaded into I2CxADB1 with the R/W bit clear, while the address low byte is loaded into I2CxADB0. I2CxCNT is loaded with the total number of data bytes to transmit, and the first data byte is loaded into I2CxTXB. After these registers are loaded, software must set the Start bit to begin communication.
   2. 1.2.When ABD is set (ABD = 1), the address buffers are disabled. In this case, I2CxCNT must be loaded with the total number of bytes to transmit prior to loading I2CxTXB with the address high byte and R/W bit. A write to I2CxTXB forces module hardware to issue a Start condition automatically; software writes to the S bit are ignored.
2. 2.Master hardware waits for BFRE to be set, then shifts out the Start condition. Module hardware sets the Master Mode Active (MMA) bit and the Start Condition Interrupt Flag (SCIF). If the Start Condition Interrupt Enable (SCIE) bit is also set, the generic I2CxIF is also set.
3. 3.Master hardware transmits the address high byte and R/W bit from I2CxADB1.
4. 4.Master hardware transmits the 9th clock pulse and shifts in the ACK/NACK response from the slave.

   If the master receives a NACK, it issues a Stop condition.

   If the master receives and ACK and:

   1. 4.1.ABD = 0: Hardware transmits the address low byte from I2CxADB0.
   2. 4.2.ABD = 1: Hardware sets I2CxTXIF and the Master Data Request (MDR) bit and waits for software to load I2CxTXB with the address low byte. Software must load I2CxTXB to resume communication.
5. 5.If upon the 8th falling edge of SCL I2CxTXB is empty (TXBE = 1), I2CxCNT is non-zero (I2CxCNT != 0), and the Clock Stretching Disable (CSD) bit is clear (CSD = 0):
   • I2CxTXIF is set. If the I²C Transmit Interrupt Enable (I2CxTXIE) bit is also set, the generic I2CxIF is also set.
   • MDR bit is set and the clock is stretched, allowing time for software to load I2CxTXB with the address low byte. Once I2CxTXB has been written, hardware releases SCL and clears MDR.
6. 6.Hardware transmits the 9th clock pulse and waits for an ACK/NACK response from the slave. If the master receives an ACK, module hardware transfers the data from I2CxTXB into the transmit shift register and I2CxCNT is decremented by one. If the master receives a NACK, hardware will attempt to issue a Stop condition. If the clock is currently being stretched by a slave, the master must wait until the bus is free before issuing the Stop.
7. 7.Master hardware checks I2CxCNT for a zero value. If I2CxCNT is zero:
   1. 7.1.If ABD is clear (ABD = 0), master hardware issues a Stop condition, or sets MDR if the Restart Enable (RSEN) bit is set and waits for software to set the Start bit to issue a Restart condition. CNTIF is set.
   2. 7.2.If ABD is set (ABD = 1), master hardware issues a Stop condition, or sets MDR if RSEN is set and waits for software to load I2CxTXB with a new slave address. CNTIF is set.
8. 8.Master hardware transmits the data byte.
9. 9.If upon the 8th falling edge of SCL I2CxTXB is empty (TXBE = 1), I2CxCNT is non-zero (I2CxCNT != 0), and CSD is clear (CSD = 0):
   • The I2CxTXIF bit is set. If the I2CxTXIE bit is also set, the generic I2CxIF is also set.
   • The MDR bit is set, and the clock is stretched, allowing time for software to load I2CxTXB with new data. Once I2CxTXB has been written, hardware releases SCL and clears MDR.
   If TXBE is set (TXBE = 1) and I2CxCNT is zero (I2CxCNT = 0):
   • I2CxTXIF is NOT set.
   • CNTIF is set.
   • Master hardware issues a Stop condition, setting PCIF.
10. 10.Repeat Steps 6 – 9 until all data has been transmitted.

Figure 1. 10-Bit Master Mode Transmission