Slave Reception (10-Bit Addressing Mode)

The following section describes the sequence of events that occur when the module is receiving data in 7-bit Addressing mode:

1. 1.The master issues a Start condition. Once the Start is detected, slave hardware sets the Start Condition Interrupt Flag (SCIF) bit. If the Start Condition Interrupt Enable (SCIE) bit is also set, the generic I2CxIF bit is also set.
2. 2.Master hardware transmits the address high byte with the R/W bit clear (R/W = 0).
3. 3.The received high address byte is compared to the values in the I2CxADR registers. If the slave is configured in 10-bit Addressing mode (no masking), the received high address byte is compared to the values in the I2CxADR1 and I2CxADR3 registers. If the slave is configured in 10-bit Addressing with Masking mode, the received high address byte is compared to the masked value in the I2CxADR1 register.

   If a high address match occurs:

   • The R/W bit value is copied to the Read Information (R) bit by module hardware.
   • The Data (D) bit is cleared (D = 0) by hardware, indicating the last received byte was an address.
   • The Address Interrupt Flag (ADRIF) bit is set (ADRIF = 1). It is important to note that regardless of whether the Address Interrupt and Hold Enable (ADRIE) bit is set, clock stretching does not occur when the R/W bit is clear in 10-bit Addressing modes.
   • The matching address is loaded into either the I2CxADB1 register or into the I2CxRXB register as determined by the Address Buffer Disable (ABD) bit. When ABD is clear (ABD = 0), the matching address is copied to I2CxADB1. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets the Receive Buffer Full Status (RXBF) bit and the I²C Receive Interrupt Flag (I2CxRXIF) bit.

   If no address match occurs, the module remains idle.

4. 4.The master device transmits the 9th clock pulse and slave hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive buffer overflow (RXO = 1), slave hardware generates a NACK and the module goes idle.
5. 5.The master device transmits the low address byte. If the slave is configured in 10-bit Addressing mode (no masking), the received low address byte is compared to the values in I2CxADR0 and I2CxADR2. In 10-bit Addressing with Masking mode, the received low address byte is compared to the masked value of I2CxADR0.

   If a match occurs:

   • The Slave Mode Active (SMA) bit is set by module hardware.
   • ADRIF is set. If ADRIE is set, and the Clock Stretching Disable (CSD) bit is clear, hardware sets the Slave Clock Stretching (CSTR) bit and the generic I2CxIF bit. This allows time for the slave to read either I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the slave has finished processing the address, software must clear CSTR to resume operation.
   • The matching received address is loaded into either the I2CxADB0 register or into the I2CxRXB register as determined by the ABD bit. When ABD is clear (ABD = 0), the matching address is copied to I2CxADB0. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets the RXBF and the I2CxRXIF bits. I2CxRXIF is a read-only bit and must be cleared by either reading I2CxRXB or by setting the Clear Buffer (CLRBF) bit (CLRBF = 1).

   If no match occurs, the module goes idle.

6. 6.The master device transmits the 9th clock pulse and slave hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive buffer overflow (RXO = 1), slave hardware generates a NACK and the module goes idle.
7. 7.After the 9th falling edge of SCL, the Acknowledge Status Time Interrupt Flag (ACKTIF) bit is set. If the Acknowledge Time Interrupt and Hold Enable (ACKTIE) bit is also set, the generic I2CxIF is set, and if slave hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0). If a NACK was generated, the CSTR bit remains unchanged. Once completed, software must clear CSTR and ACKTIF to release the clock and resume operation.
8. 8.If slave hardware generated a NACK, master hardware generates a Stop condition, the Stop Condition Interrupt Flag (PCIF) is set when slave hardware detects the Stop condition, and the slave goes idle. If an ACK was generated, master hardware transmits the first seven bits of the 8-bit data byte.
9. 9.If data remains in I2CxRXB (RXBF = 1 and I2CxRXIF = 1) when the first seven bits of the new byte are received by the shift register, CSTR is set, and if CSD is clear, the clock is stretched after the 7th falling edge of SCL. This allows time for the slave to read I2CxRXB, which clears RXBF and I2CxRXIF, and prevents a receive buffer overflow. Once I2CxRXB has been read, RXBF and I2CxRXIF are cleared and hardware releases SCL.
10. 10.Master hardware transmits the 8th bit of the current data byte into the slave receive shift register. Slave hardware then transfers the complete byte into I2CxRXB on the 8th falling edge of SCL and sets the following bits:
    • I2CxRXIF
    • I2CxIF
    • Data Write Interrupt Flag (WRIF)
    • Data (D)
    • RXBF
    I2CxCNT is decremented by one. If the Data Write Interrupt and Hold Enable (WRIE) bit is set (WRIE = 1), hardware sets CSTR (when CSD = 0) and stretches the clock, allowing time for slave software to read I2CxRXB and determine the state of the ACKDT bit that is transmitted back to the master. Once the slave determines the acknowledgement response, software clears CSTR to allow further communication.
11. 11.Upon the 9th falling edge of SCL, the ACKTIF bit is set. If ACKTIE is also set, the generic I2CxIF is set, and if CSD is clear, slave hardware sets CSTR and stretches the clock. This allows time for software to read I2CxRXB. Once complete, software must clear both CSTR and ACKTIF to release the clock and continue communication.
12. 12.Repeat Steps 8 – 11 until the master has transmitted all the data (I2CxCNT = 0), or until the master issues a Stop or Restart condition.

Figure 1. 10-Bit Slave Mode Reception