| General: | |
| Introduced the new product family name: Atmel | SMART Removed references to Clock Failure Detection. Sub sections within chapters might been moved to other location within the chapter. Typo corrections. |
|
| Configuration Summary | |
| Added 32KB Flash and 4KB SRAM options to SAM D21J and SAM D21G. | |
| Ordering Information | |
| Added Tray to Carrier Type option for SAM D21E, SAMD 21G and SAMD21J ordering codes. | |
| I/O Multiplexing and Considerations: | |
| Updated REF
function on PA03 and PA04 in Table 1: PA03: DAC/VREFP changed to DAC/VREFA. PA04: ADC VREFP changed to ADC/VREFB. Updated COM function on PA30 and PA31: PA30: CORTEX_M0P/SWCLK changed to SWCKL. PA31: Added SWDIO. |
|
| Memories | |
| Added a
second note to Table 2. Added Figure 1 Calibration and Auxiliary Space. Added default values for fuses in Table 1 NVM User Row Mapping. |
|
| Processor And Architecture | |
| MTB renamed from “Memory Trace Buffer” to “Micro Trace Buffer”. | |
| DSU - Device Service Unit | |
| Updated
description of Starting CRC32 Calculation. Updated title of Table 1. Added Device Selection table (Table 1) to Device Selection bit description the Device Identification register (DID.DEBVSEL). |
|
| GCLK - Generic Clock Controller | |
| Signal names updated in Device Clocking Diagram, Block Diagram. | |
| PM – Power Manager | |
| Added figure
Figure 1. Register Summary: Removed CFD bit from INTENCLR, INTENSET and INTFLAG. Added PTC bit to APBCMASK register. Register Description: AHB Mask register (AHBMASK): Full bit names updated. APBC Mask register (APBCMASK.PTC): Added PTC to bit 19. CFD bit removed from INTENCLR, INTENSET and INTFLAG. |
|
| SYSCTRL – System Controller | |
| Updated
description of 8MHz Internal Oscillator (OSC8M) Operation. FDPLL96M section reorganized and more integrated in the SYSCTRL chapter: Features, Signal Description and Product Dependencies sub sections removed and integrated with the corresponding sections in SYSCTRL. Register Summary: Added VREG register on address 0x3C - 0x3D. Register Description: Updated reset values in OSC8M. Updated CALIB[11:0] bit description in OSC8M. Updated LBYPASS bit description in DPLLCTRLB. |
|
| WDT – Watchdog Timer | |
| Updated
description in Principle of Operation: Introducing the bits used in Table 1. Updated description in Initialization. Updated description in Normal Mode. Updated description in Window Mode. Updated description in Interrupts. WEN bit description in the Control register (CTRL.WEN) updated with information on enable-protection. |
|
| RTC – Real-Time Counter | |
| Periodic Events: Bit names updated fro, PERx to PEREOx in
example, Figure 1. CLOCK.HOUR[4:0]: Updated Table 1 Mode 0 and Mode 2: CMPx bit renamed to CMP0 since only one CMP0 is available. Bit description of CLOCK.HOUR[4:0]: Updated Table 1 ALARMn register renamed to ALARM0. |
|
| DMAC – Direct Memory Access Controller | |
| Updated block
diagram, Block Diagram. General updated description. |
|
| EIC – External Interrupt Controller | |
| Register
Summary and Register Description: EVCTRL register: Added bits EXTINTO17 and EXTINTO16 in bit position 17 and 16 respectively. INTENCLR, INTENSET, INTENFLAG registers: Added bits EXTINT17 and EXTINT16 in bit position 17 and 16 respectively. WAKEUP register: Added bits WAKEUPEN17 and WAKEUPEN16 in bit position 17 and 16 respectively. CONFIG2 register added, CONFIG0 and CONFIG1 registers updated: Added bits FILTEN0...31 and SENSE0...31. |
|
| NVMCTRL – Non-Volatile Memory Controller | |
| CTRLB register: Removed table from NVM Read Wait States description (RWS[3:0]) | |
| PORT - I/O Pin Controller | |
| Instances of
the term “pad” replaced with “pin”. Instances of the term “bundle” replaced with “group” and “interface”. Basic Operation description updated. Peripheral Multiplexing n (PMUX0) register: Offset formula updated. |
|
| EVSYS – Event System | |
| Updated
information in Features. Power Management updated: Description of on how event generators can generate an event when the system clock is stopped moved to Sleep Mode Operation. Clocks updated: Renamed EVSYS channel dedicated generic clock from GCLK_EVSYS_x to GCLK_EVSYS_CHANNELx. Updated description in Principle of Operation. Updated description in sub sections of Basic Operation. Updated description in The Overrun Channel n Interrupt. Channel x Overrun bit description in INTFLAG updated. |
|
| SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter | |
| Updated
description in Break Character Detection and Auto-Baud. Updated description in Start-of-Frame Detection. |
|
| I2S - Inter-IC Sound Controller | |
| Introducing
Frame Synch Clock. Signal Description: Added separate tables for Master-, Slave- and Controller mode. Updated description in Debug Operation and Register Access Protection. Updated description in Principle of Operation. Updated description in sub sections of Basic Operation. Updated formula in MCKn Clock Frequency. Updated formulas in Relation Between MCKn, SCKn, and Sampling Frequency fs. Updated description in PDM Reception. Section on MONO removed and information included in Basic Operation. Updated property of Control A (CTRLA) register: Added Write-Synchronized |
|
| TCC – Timer/Counter for Control Applications | |
| Updated
description in Principle of Operation. Updated description in sub sections of Basic Operation. Updated description in sub sections of Additional Features. Updated description in Synchronization. Lock Update (LUPD) bit description updated in Control B Clear (CTRLBCLR) register. Compare Channel Buffer x Busy (CCBx) bit description updated in Synchronization Busy (SYNCBUSY) register. Event Control (EVCTRL) register property updated: Removed Enable-Protected. Interrupt Enable Clear (INTENCLR), Interrupt Enable Set (INTENSET) and Interrupt Flag Status and Clear (INTFLAG) registers: Updated bit description of FAULT0, FAULT1, FAULTA and FAULTB. STATUS register bit descriptions updated. Wave Control (WAVE) register property updated: Removed Read-Synchronized. Pattern Buffer (PATTB) register: Updated property and bit description. Waveform Control Buffer (WAVEB) register: Updated property and bit descriptions. |
|
| USB – Universal Serial Bus | |
| Removed
figures: Setup Transaction Overview, OUT Single Bank Transaction Overview, IN
Single Bank Transaction Overview and USB Host Communication Flow. Updated description and graphics in sub sections of USB Device Operations. Updated description in sub sections of Host Operations. Pad Calibration (PADCAL) register: Access updated. Upgraded bit descriptions. Pipe Descriptor Structure: Updated register reset values. |
|
| ADC – Analog-to-Digital Converter | |
| Register
Description: REFCTRL bit selection names updated from AREFA / AREFB to VREFA / VREFB in Table 1 |
|
| DAC – Digital-to-Analog Converter | |
| Updated block diagram and signal description: VREFP replaced with VREFB. | |
| Electrical Characteristics | |
| Updated VDD max from 3.63V to
3.63V in Absolute Maximum Ratings. Updated VDDIN pin from 57 to 56 in GPIO Clusters. Power Consumption: Updated Max values for STANDBY from 190.6μA and 197.3μA to 100μA in Table 1. Added Peripheral Power Consumption. I/O Pin Characteristics: tRISE and tFALL updated with different load conditions depending on the DVRSTR value in . I/O Pin Characteristics: Correct typo IOL and IOH Max values inverted between PORT.PINCFG.DRVSTR=0 and 1, tRISE and tFALL updated with different load conditions depending on the DVRSTR value in Table 1. Analog Characteristics: Removed note from Table 2. Analog-to-Digital (ADC) characteristics: Added Max DC supply current (IDD), RSAMPLE maximum value changed from 2.8kW to 3.5kW, Conversion time Typ value change to Min Value in Table 1. Digital to Analog Converter (DAC) Characteristics: Added Max DC supply current (IDD) in Table 1. Analog Comparator Characteristics: Added Min and Max values for VSCALE INL, DNL, Offset Error and Gain Error in Table 1. Internal 1.1V Bandgap Reference Characteristics: Added Min and Max values, removed accuracy row in Table 1. SERCOM in I2C Mode Timing: Add Typical values for tR in Table 1. Removed Asynchronous Watchdog Clock Characterization. 32.768kHz Internal oscillator (OSC32K) Characteristics: Added Max current consumption (IOSC32K) in Table 1. Updated Crystal Oscillator Characteristics (XOSC32K) ESR maximum values, Crystal Oscillator Characteristics. Updated Crystal Oscillator Characteristics (XOSC) ESR maximum value, Crystal Oscillator Characteristics from 348kΩ to 141kΩ. Digital Frequency Locked Loop (DFLL48M) Characteristics: Updated presentation, now separating between Open- and Closed Loop Modes. Added fREF Min and Max values to Table 1. Updated typical Startup time ( tSTARTUP) from 6.1µs to 8µs in Table 2. Updated typical Fine lock time (tLFINE) from 700µs to 600µs in Table 2. Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added Current consumption (IFDPLL96M), Period Jitter (Jp), Lock time (tLOCK), Duty cycles parameters in Table 1. Added USB Characteristics. Timing Characteristics: Added SCK period (tSCK) Typ value in Table 1. |
|
| Errata | |
| Errata for revision B added. | |